The present invention generally relates to vertical field effect transistors (FETs). More specifically, the present invention relates to vertical FETs (VFETs) with uniform threshold voltage (Vt).
Non-planar transistors such as VFETs can achieve a reduced FET device footprint without compromising FET device performance characteristics. In VFETs the source-drain current flows in a direction perpendicular to a major surface of the substrate. For example, in a known VFET configuration, the substrate surface is horizontal and a vertical fin or nanowire extends upward from the substrate surface. The fin or nanowire forms the channel region of the transistor. Source and drain regions are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin or nanowire sidewalls.